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IEEEINTERACT
2002
IEEE
13 years 12 months ago
Code Cache Management Schemes for Dynamic Optimizers
A dynamic optimizer is a software-based system that performs code modifications at runtime, and several such systems have been proposed over the past several years. These systems ...
Kim M. Hazelwood, Michael D. Smith
IEEEPACT
2006
IEEE
14 years 1 months ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
ISCAPDCS
2003
13 years 8 months ago
N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
Aleksandar Milenkovic, Milena Milenkovic, Jeffrey ...
ICCD
2007
IEEE
139views Hardware» more  ICCD 2007»
14 years 4 months ago
Statistical simulation of chip multiprocessors running multi-program workloads
This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to ...
Davy Genbrugge, Lieven Eeckhout
ICIP
1998
IEEE
14 years 8 months ago
An Efficient Motion Estimation Algorithm based on Tracing Techniques on Large Search Windows
Motion estimation represents the most computationally intensive task for all efficient motion compensated compression standards. This fact, despite the several eflorts aiming at r...
Marco Mattavelli, Giorgio Zoia