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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 11 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
NIS
1998
131views more  NIS 1998»
13 years 7 months ago
Dynamic Memory Allocation for Large Query Execution
The execution time of a large query depends mainly on the memory utilization which should avoid disk accesses for intermediate results. Poor memory management can hurt performance ...
Luc Bouganim, Olga Kapitskaia, Patrick Valduriez
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
13 years 11 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
EOR
2006
76views more  EOR 2006»
13 years 7 months ago
Load balancing and capacity constraints in a hierarchical location model
Recent work on the location of perinatal facilities in the municipality of Rio de Janeiro resulted in the development of an uncapacitated, three-level hierarchical model. An impor...
Roberto D. Galvão, Luis Gonzalo Acosta Espe...
MICRO
1997
IEEE
82views Hardware» more  MICRO 1997»
13 years 11 months ago
Procedure Based Program Compression
Cost and power consumption are two of the most important design factors for many embedded systems, particularly consumer devices. Products such as Personal Digital Assistants, pag...
Darko Kirovski, Johnson Kin, William H. Mangione-S...