Sciweavers

287 search results - page 10 / 58
» The Case for a Single-Chip Multiprocessor
Sort
View
CAL
2006
13 years 8 months ago
A case for fault tolerance and performance enhancement using chip multi-processors
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
Huiyang Zhou
CASES
2003
ACM
14 years 1 months ago
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Peter Poplavko, Twan Basten, Marco Bekooij, Jef L....
HPCA
2007
IEEE
14 years 8 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
LCPC
2000
Springer
14 years 4 hour ago
Automatic Coarse Grain Task Parallel Processing on SMP Using OpenMP
This paper proposes a simple and efficient implementation method for a hierarchical coarse grain task parallel processing scheme on a SMP machine. OSCAR multigrain parallelizing c...
Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka
TPDS
2008
134views more  TPDS 2008»
13 years 7 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...