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» The Case for a Single-Chip Multiprocessor
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IPPS
2000
IEEE
14 years 25 days ago
Using Time Skewing to Eliminate Idle Time due to Memory Bandwidth and Network Limitations
Time skewing is a compile-time optimization that can provide arbitrarily high cache hit rates for a class of iterative calculations, given a sufficient number of time steps and s...
David Wonnacott
ICDCS
1995
IEEE
14 years 8 hour ago
Parallel Processing on Networks of Workstations: A Fault-Tolerant, High Performance Approach
One of the mostsoughtaftersoftware innovation of thisdecade is the construction of systems using off-the-shelf workstations that actually deliver, and even surpass, the power and ...
Partha Dasgupta, Zvi M. Kedem, Michael O. Rabin
IEEEPACT
2009
IEEE
14 years 3 months ago
Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
Leo Porter, Bumyong Choi, Dean M. Tullsen
ACRI
2006
Springer
14 years 2 months ago
Parallel Simulation of Asynchronous Cellular Automata Evolution
For simulating physical and chemical processes on molecular level asynchronous cellular automata with probabilistic transition rules are widely used being sometimes referred to as ...
Olga L. Bandman
SRDS
2003
IEEE
14 years 1 months ago
Transparent Fault-Tolerant Java Virtual Machine
Replication is one of the prominent approaches for obtaining fault tolerance. Implementing replication on commodity hardware and in a transparent fashion, i.e., without changing t...
Roy Friedman, Alon Kama