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ICCAD
2007
IEEE
140views Hardware» more  ICCAD 2007»
14 years 7 months ago
Thermal-aware Steiner routing for 3D stacked ICs
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
Mohit Pathak, Sung Kyu Lim
ICCAD
2004
IEEE
138views Hardware» more  ICCAD 2004»
14 years 7 months ago
A thermal-driven floorplanning algorithm for 3D ICs
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
Jason Cong, Jie Wei, Yan Zhang
ICCAD
2002
IEEE
129views Hardware» more  ICCAD 2002»
14 years 7 months ago
Transmission line design of clock trees
We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations pr...
Rafael Escovar, Roberto Suaya
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
14 years 4 months ago
Dynamic thermal management in 3D multicore architectures
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
Ayse Kivilcim Coskun, José L. Ayala, David ...
DATE
2009
IEEE
95views Hardware» more  DATE 2009»
14 years 4 months ago
Minimization of NBTI performance degradation using internal node control
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
David R. Bild, Gregory E. Bok, Robert P. Dick