244 search results - page 4 / 49 » The Design and Analysis of a Cache Architecture for Texture ... |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
MSE
2002
IEEE
14 years 11 days ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
ADHOC
2007
13 years 7 months ago
2007
Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congest...