Sciweavers

27 search results - page 4 / 6
» The Design and Evaluation of Policy-Controllable Buffer Cach...
Sort
View
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
PASTE
2010
ACM
14 years 17 days ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
ICDCS
2007
IEEE
14 years 1 months ago
STEP: Sequentiality and Thrashing Detection Based Prefetching to Improve Performance of Networked Storage Servers
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
Shuang Liang, Song Jiang, Xiaodong Zhang
ISCA
2002
IEEE
123views Hardware» more  ISCA 2002»
14 years 13 days ago
Going the Distance for TLB Prefetching: An Application-Driven Study
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
Gokul B. Kandiraju, Anand Sivasubramaniam
DATE
2002
IEEE
100views Hardware» more  DATE 2002»
14 years 14 days ago
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose