619 search results - page 82 / 124 » The Design and Implementation of a Certifying Compiler |
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
MEMOCODE
2003
IEEE
14 years 2 months ago
2003
IEEE
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
ISLPED
2003
ACM
14 years 2 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
LCTRTS
2010
Springer
14 years 3 months ago
2010
Springer
We describe the extension of a reactive programming language with a behavioral contract construct. It is dedicated to the programming of reactive control of applications in embedd...
IEEEPACT
2007
IEEE
14 years 3 months ago
2007
IEEE
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...