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» The Design and Performance of a Conflict-Avoiding Cache
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FPL
2005
Springer
131views Hardware» more  FPL 2005»
15 years 11 months ago
An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications
Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is requir...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
PASTE
2010
ACM
15 years 11 months ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
VIS
2007
IEEE
101views Visualization» more  VIS 2007»
16 years 7 months ago
Random-Accessible Compressed Triangle Meshes
With the exponential growth in size of geometric data, it is becoming increasingly important to make effective use of multilevel caches, limited disk storage, and bandwidth. As a r...
Sung-Eui Yoon, Peter Lindstrom
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
15 years 11 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth
CODES
1998
IEEE
15 years 10 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...