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» The Design and Performance of a Conflict-Avoiding Cache
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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 1 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
ISCA
2006
IEEE
121views Hardware» more  ISCA 2006»
14 years 1 months ago
Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors
A simple and low-cost approach to supporting snoopy cache coherence is to logically embed a unidirectional ring in the network of a multiprocessor, and use it to transfer snoop me...
Karin Strauss, Xiaowei Shen, Josep Torrellas
MICRO
2006
IEEE
103views Hardware» more  MICRO 2006»
14 years 1 months ago
NoSQ: Store-Load Communication without a Store Queue
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
Tingting Sha, Milo M. K. Martin, Amir Roth
ACMSE
2005
ACM
14 years 29 days ago
Exploring communication overheads and locking policies in a peer-to-peer synchronous collaborative editing system
In this paper, we describe recent work in developing a peer-topeer collaborative environment. The study examines various locking mechanisms/policies by adjusting the granularity o...
Jon A. Preston, Sushil K. Prasad
EUROPAR
2005
Springer
14 years 28 days ago
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to ...
Alberto Ros, Manuel E. Acacio, José M. Garc...