867 search results - page 155 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
135
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ISCA
2006
IEEE
15 years 11 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
141
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ISCA
2006
IEEE
15 years 11 months ago
2006
IEEE
A simple and low-cost approach to supporting snoopy cache coherence is to logically embed a unidirectional ring in the network of a multiprocessor, and use it to transfer snoop me...
147
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MICRO
2006
IEEE
15 years 11 months ago
2006
IEEE
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
161
Voted
ACMSE
2005
ACM
15 years 11 months ago
2005
ACM
In this paper, we describe recent work in developing a peer-topeer collaborative environment. The study examines various locking mechanisms/policies by adjusting the granularity o...
170
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EUROPAR
2005
Springer
15 years 11 months ago
2005
Springer
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to ...