Sciweavers

867 search results - page 16 / 174
» The Design and Performance of a Conflict-Avoiding Cache
Sort
View
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 2 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
HIPEAC
2010
Springer
13 years 6 months ago
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iri...
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
14 years 2 months ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt
SIGMETRICS
2000
ACM
147views Hardware» more  SIGMETRICS 2000»
13 years 8 months ago
High-capacity Internet middleware: Internet caching system architectural overview
Previous studies measuring the performance of general-purpose operating systems running large-scale Internet server applications, such as proxy caches, have identified design defi...
Gary Tomlinson, Drew Major, Ron Lee
DAC
2003
ACM
14 years 1 months ago
Improved indexing for cache miss reduction in embedded systems
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
Tony Givargis