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» The Design and Performance of a Conflict-Avoiding Cache
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SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
14 years 1 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel
EDBT
2006
ACM
157views Database» more  EDBT 2006»
14 years 8 months ago
Caching Complementary Space for Location-Based Services
In this paper, we propose a novel client-side, multi-granularity caching scheme, called "Complementary Space Caching" (CS caching), for location-based services in mobile ...
Ken C. K. Lee, Wang-Chien Lee, Baihua Zheng, Jianl...
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 1 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
ECRTS
2009
IEEE
13 years 6 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
CODES
2011
IEEE
12 years 8 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu