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WOSP
2010
ACM
14 years 3 months ago
Reducing performance non-determinism via cache-aware page allocation strategies
Performance non-determinism in computer systems complicates evaluation, use, and even development of these systems. In performance evaluation via benchmarking and simulation, nond...
Michal Hocko, Tomás Kalibera
CASCON
2004
127views Education» more  CASCON 2004»
13 years 10 months ago
A quantitative analysis of the performance impact of specialized bytecodes in java
Java is implemented by 201 bytecodes that serve the same purpose as assembler instructions while providing object-file platform independence. A collection of core bytecodes provid...
Ben Stephenson, Wade Holst
DAC
2009
ACM
14 years 9 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
DAC
2004
ACM
14 years 9 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
14 years 5 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang