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CODES
2006
IEEE
14 years 2 months ago
Thermal-aware high-level synthesis based on network flow method
Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reli...
Pilok Lim, Taewhan Kim
GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
PLDI
2003
ACM
14 years 2 months ago
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
This paper presents the design and implementation of a compiler algorithm that effectively optimizes programs for energy usage using dynamic voltage scaling (DVS). The algorithm ...
Chung-Hsing Hsu, Ulrich Kremer
FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
14 years 1 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
ISCA
2002
IEEE
123views Hardware» more  ISCA 2002»
14 years 1 months ago
Going the Distance for TLB Prefetching: An Application-Driven Study
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
Gokul B. Kandiraju, Anand Sivasubramaniam