Sciweavers

113 search results - page 19 / 23
» The Drill Down Benchmark
Sort
View
HPCA
2005
IEEE
14 years 9 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
PPOPP
2010
ACM
14 years 3 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...
IEEEPACT
2008
IEEE
14 years 3 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
SEMWEB
2007
Springer
14 years 2 months ago
Change Paths in Reasoning!
Millions of research funding has been put down to develop - what I call - old forms - of reasoning that are characterized by strong focus on theoretical properties and strict adher...
Raphael Volz
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
14 years 2 months ago
A novel framework for multilevel full-chip gridless routing
— Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult ...
Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin