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» The Dynamic Enterprise Bus
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IPPS
2006
IEEE
14 years 2 months ago
Analysis of a reconfigurable network processor
In this paper an analysis of a dynamically reconfigurable processor is presented. The network processor incorporates a processor and a number of coprocessors that can be connected...
Christopher Kachris, Stamatis Vassiliadis
CODES
2003
IEEE
14 years 1 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
DAC
2005
ACM
13 years 10 months ago
Sign bit reduction encoding for low power applications
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
ICC
2008
IEEE
183views Communications» more  ICC 2008»
14 years 2 months ago
An Autonomic Service Delivery Platform for Service-Oriented Network Environments
CALLAWAY, ROBERT DAVID. An Autonomic Service Delivery Platform for Service-Oriented Network Environments. (Under the direction of Michael Devetsikiotis and Yannis Viniotis.) Servi...
Robert D. Callaway, Michael Devetsikiotis, Yannis ...
ICCAD
2002
IEEE
124views Hardware» more  ICCAD 2002»
14 years 5 months ago
Interface specification for reconfigurable components
This paper presents a way of encoding some kinds of dynamic reconfiguration behaviour in the interface portion of circuit descriptions. This has many advantages. The user of a rec...
Satnam Singh