100 search results - page 12 / 20 » The Effect of Instruction Set Complexity on Program Size and... |
MICRO
2002
IEEE
13 years 11 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
ISCA
2005
IEEE
14 years 9 days ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
ASAP
2008
IEEE
13 years 8 months ago
2008
IEEE
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
ICALP
2009
Springer
14 years 7 months ago
2009
Springer
We initiate the study of sublinear-time algorithms in the external memory model [14]. In this model, the data is stored in blocks of a certain size B, and the algorithm is charged...