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LCTRTS
2009
Springer
14 years 5 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 5 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
SAC
2006
ACM
13 years 10 months ago
A new method of generating synchronizable test sequences that detect output-shifting faults based on multiple UIO sequences
The objective of testing is to determine the conformance between a system and its specification. When testing distributed systems, the existence of multiple testers brings out the...
Kai Chen, Fan Jiang, Chuan-dong Huang
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
14 years 5 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 8 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...