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» The Energy Efficiency of IRAM Architectures
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GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
INFOVIS
2003
IEEE
14 years 27 days ago
Developing Architectural Lighting Representations
This paper reports on the development of a visualization system for architectural lighting designers. It starts by motivating the problem as both complex in its physics and social...
Daniel C. Glaser, Roger Tan, John F. Canny, Ellen ...
DATE
2004
IEEE
133views Hardware» more  DATE 2004»
13 years 11 months ago
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration...
Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
CAL
2008
13 years 7 months ago
Hierarchical Instruction Register Organization
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and ...
David Black-Schaffer, James D. Balfour, William J....
JEC
2006
88views more  JEC 2006»
13 years 7 months ago
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
John Oliver, Ravishankar Rao, Diana Franklin, Fred...