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FPL
2010
Springer
155views Hardware» more  FPL 2010»
13 years 5 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber
GECCO
2010
Springer
170views Optimization» more  GECCO 2010»
14 years 14 days ago
Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution
Technology scaling has offered advantages to embedded systems, such as increased performance, more available memory and reduced energy consumption. However, scaling also brings a...
José Manuel Colmenar, José L. Risco-...
CSE
2009
IEEE
14 years 2 months ago
Performance Analysis of an HMM-Based Gesture Recognition Using a Wristwatch Device
—Interaction with mobile devices that are intended for everyday use is challenging since such systems are continuously optimized towards small outlines. Watches are a particularl...
Roman Amstutz, Oliver Amft, Brian French, Asim Sma...
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
14 years 2 months ago
Disaggregated memory for expansion and sharing in blade servers
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Part...
HPCA
2001
IEEE
14 years 8 months ago
A New Scalable Directory Architecture for Large-Scale Multiprocessors
The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm unfeasible for very la...
Manuel E. Acacio, José González, Jos...