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ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 11 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
ISLPED
2007
ACM
110views Hardware» more  ISLPED 2007»
13 years 11 months ago
A 0.4-V UWB baseband processor
A 0.4-V UWB digital baseband processor has been fabricated in a standard-VT 90-nm CMOS technology. The baseband processor operates at an ultra-low supply voltage to reduce energy ...
Vivienne Sze, Anantha P. Chandrakasan
JCP
2008
324views more  JCP 2008»
13 years 9 months ago
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
Keivan Navi, Omid Kavehie, Mahnoush Rouholamini, A...
SIAMJO
2008
110views more  SIAMJO 2008»
13 years 9 months ago
Subdifferential Calculus Rules in Convex Analysis: A Unifying Approach Via Pointwise Supremum Functions
We provide a rule to calculate the subdifferential of the pointwise supremum of an arbitrary family of convex functions defined on a real locally convex topological vector space. ...
Abderrahim Hantoute, Marco A. López, Consta...
ICASSP
2011
IEEE
13 years 1 months ago
Real-time DVB-S2 LDPC decoding on many-core GPU accelerators
It is well known that LDPC decoding is computationally demanding and one of the hardest signal operations to parallelize. Beyond data dependencies that restrict the decoding of a ...
Gabriel Falcão Paiva Fernandes, Joao Andrad...