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CCGRID
2005
IEEE
14 years 1 months ago
Enabling technologies for future learning scenarios: the semantic grid for human learning
In this paper, starting from the limitations and constrains of traditional human learning approaches, we outline new suitable approaches to education and training in future knowle...
Angelo Gaeta, Pierluigi Ritrovato, Francesco Orciu...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
DSD
2007
IEEE
132views Hardware» more  DSD 2007»
13 years 11 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge
HICSS
2002
IEEE
68views Biometrics» more  HICSS 2002»
14 years 17 days ago
Framing Virtual Interactivity between Government and Citizens: A Study of Feedback Systems in the Chicago Police Department
This paper considers the current efforts to describe the effect of Internet-based technology on interactivity between citizens and public organizations to be incomplete and poorly...
Shelley Fulla, Eric W. Welch
DATE
2008
IEEE
129views Hardware» more  DATE 2008»
14 years 2 months ago
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications
Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length,...
Dinesh Pamunuwa