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LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
RTA
2007
Springer
14 years 1 months ago
The Termination Competition
The third Termination Competition took place in June 2006. We present the background, results and conclusions of this competition. 1 Motivation and history In the past decades seve...
Claude Marché, Hans Zantema
SAMOS
2007
Springer
14 years 1 months ago
Online Prediction of Applications Cache Utility
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
Miquel Moretó, Francisco J. Cazorla, Alex R...
CGO
2006
IEEE
14 years 1 months ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn
DATE
2006
IEEE
78views Hardware» more  DATE 2006»
14 years 1 months ago
Wireless sensor networks and beyond
—Wireless Sensor Networks provide opportunities even outside their usual application domain of environmental monitoring. In this paper we present a case study on the use of Wirel...
Paul J. M. Havinga
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