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VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
14 years 10 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
DCC
2002
IEEE
14 years 9 months ago
Globally Optimal Uneven Error-Protected Packetization of Scalable Code Streams
In this paper, we present a family of new algorithms for rate-fidelity optimal packetization of scalable source bit streams with uneven error protection. In the most general settin...
Sorina Dumitrescu, Xiaolin Wu, Zhe Wang
SEMCO
2009
IEEE
14 years 4 months ago
Towards a Global Business Document Reference Ontology
In the field of business document standardization a multitude of different standardization efforts exist. Unfortunately, most of the developed standards are designed for a speci...
Philipp Liegl, Christian Huemer, Marco Zapletal
NOCS
2009
IEEE
14 years 4 months ago
Silicon-photonic clos networks for global on-chip communication
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Sco...
CVPR
2008
IEEE
14 years 4 months ago
Global stereo reconstruction under second order smoothness priors
Second-order priors on the smoothness of 3D surfaces are a better model of typical scenes than first-order priors. However, stereo reconstruction using global inference algorithm...
Oliver J. Woodford, Philip H. S. Torr, Ian D. Reid...