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» The High Level Architecture for Simulations
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HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
RTAS
1997
IEEE
14 years 24 days ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
DAC
1996
ACM
14 years 22 days ago
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing...
Val Popescu, Bill McNamara
VTS
2000
IEEE
76views Hardware» more  VTS 2000»
14 years 29 days ago
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
Sule Ozev, Alex Orailoglu
ISPA
2004
Springer
14 years 1 months ago
Towards Correct Distributed Simulation of High-Level Petri Nets with Fine-Grained Partitioning
Abstract. Powerful grid and cluster computers allow efficient distributed simulation. Optimistic simulation techniques have been developed which allow for more parallelism in the l...
Michael Knoke, Felix Kühling, Armin Zimmerman...