2424 search results - page 152 / 485 » The High Level Architecture for Simulations |
126
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VTS
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to mitigate the problems encountered in trying to implement architectures employed in ...
145
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DAC
2004
ACM
16 years 6 months ago
2004
ACM
The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and...
169
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WSC
2008
15 years 8 months ago
2008
Testing and benchmarking of stream processing systems requires workload representative of real world scenarios with myriad of users, interacting through different applications ove...
151
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PRDC
2006
IEEE
15 years 12 months ago
2006
IEEE
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
185
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WMPI
2004
ACM
15 years 11 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...