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» The High Level Architecture for Simulations
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DELTA
2010
IEEE
15 years 11 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston
TPDS
2002
142views more  TPDS 2002»
15 years 5 months ago
MediaWorm: A QoS Capable Router Architecture for Clusters
With the increasing use of clusters in real-time applications, it has become essential to design high performance networks with Quality-of-ServiceQoS guarantees. In this paper, we...
Ki Hwan Yum, Eun Jung Kim, Chita R. Das, Aniruddha...
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
16 years 6 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
ICSOC
2003
Springer
15 years 11 months ago
Planning and Monitoring the Execution of Web Service Requests
Abstract Interaction with web services enabled marketplaces would be greatly facilitated if users were given a high level service request language to express their goals in complex...
Alexander Lazovik, Marco Aiello, Mike P. Papazoglo...
FPL
2001
Springer
88views Hardware» more  FPL 2001»
15 years 10 months ago
FPGA-Based Discrete Wavelet Transforms System
Although FPGA technology offers the potential of designing high performance systems at low cost, its programming model is prohibitively low level. To allow a novice signal/image pr...
Mokhtar Nibouche, Ahmed Bouridane, Fionn Murtagh, ...