Sciweavers

2424 search results - page 377 / 485
» The High Level Architecture for Simulations
Sort
View
VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
16 years 6 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
HPCA
2005
IEEE
16 years 6 months ago
A Unified Compressed Memory Hierarchy
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
Erik G. Hallnor, Steven K. Reinhardt
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
16 years 3 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
GLOBECOM
2006
IEEE
16 years 3 days ago
Analysis of the Effect of Mobile Terminal Speed on WLAN/3G Vertical Handovers
— WLAN hot-spots are becoming widely spread. This, combined with the availability of new multi-mode terminals integrating heterogeneous technologies, opens new business opportuni...
Telemaco Melia, Antonio de la Oliva, Ignacio Soto,...
CCGRID
2005
IEEE
15 years 11 months ago
Continuous resources allocation in Internet data centers
Internet data centers (IDCs) perform multi-customer hosting on a virtualized collection of resources while Grid computing generalizes distributed computing by focusing on large sc...
Youssef Hamadi