The current structure of the High Level Architecture (HLA) puts a tremendous burden on network load and CPU utilization for large distributed simulations due to its limited contro...
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
The paper proposes a new tool for supporting educational and professional skill development in HLA environment; the application proposed by the authors is devoted to provide a rea...
Agostino G. Bruzzone, Roberto Mosca, Roberto Revet...
The paper proposes three dimensional extension to High Level ARchitecture (HLA) and Runtime Infrastructure (RTI) to solve several issues such as security, information hiding proble...
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...