2424 search results - page 54 / 485 » The High Level Architecture for Simulations |
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
DSN
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper concerns the validity of a widely used method for estimating the architecture-level mean time to failure (MTTF) due to soft errors. The method first calculates the fai...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
RSP
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a ge...