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» The High Level Architecture for Simulations
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ASPLOS
2000
ACM
14 years 1 months ago
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop
Simulation is the primary method for evaluating computer systems during all phases of the design process. One significant problem with simulation is that it rarely models the syst...
Jeff Gibson, Robert Kunz, David Ofelt, Mark Heinri...
ITC
2003
IEEE
102views Hardware» more  ITC 2003»
14 years 2 months ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...
GECCO
2004
Springer
145views Optimization» more  GECCO 2004»
14 years 2 months ago
Search Based Automatic Test-Data Generation at an Architectural Level
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
Yuan Zhan, John A. Clark
FASE
2007
Springer
14 years 2 months ago
Scenario-Driven Dynamic Analysis of Distributed Architectures
Abstract. Software architecture constitutes a promising approach to the development of large-scale distributed systems, but architecture description languages (ADLs) and their asso...
George Edwards, Sam Malek, Nenad Medvidovic
VLSISP
2002
93views more  VLSISP 2002»
13 years 8 months ago
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Abstract. This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband proc...
Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. ...