2424 search results - page 64 / 485 » The High Level Architecture for Simulations |
ANCS
2011
ACM
12 years 8 months ago
2011
ACM
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
EUROPAR
2003
Springer
14 years 2 months ago
2003
Springer
Abstract. The Blue Gene/L supercomputer will use system-on-a-chip integration and a highly scalable cellular architecture. With 65,536 compute nodes, Blue Gene/L represents a new l...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
DAC
1996
ACM
14 years 27 days ago
1996
ACM
In this paper, we present the rst chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-speci ed input signal patterns, and thermal boundar...
VLSISP
2008
13 years 8 months ago
2008
ion of Abstract Performance Models for System-Level Design Space Exploration ANDY D. PIMENTEL, MARK THOMPSON, SIMON POLSTRA AND CAGKAN ERBAS Computer Systems Architecture Group, In...