202 search results - page 16 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ISCA
1999
IEEE
14 years 1 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
ISLPED
1999
ACM
14 years 1 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
CAL
2006
13 years 8 months ago
2006
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
In this paper, we present a methodology for low-cost and rapid context switch for multithreaded embedded processors with realtime guarantees. Context-switch, which involves saving...