202 search results - page 21 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
CGO
2004
IEEE
14 years 15 days ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
EUROPAR
1999
Springer
14 years 1 months ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
APCSAC
2005
IEEE
14 years 2 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...