202 search results - page 7 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
148
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ISCA
2002
IEEE
15 years 8 months ago
2002
IEEE
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
118
Voted
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
148
Voted
ICMCS
2006
IEEE
15 years 9 months ago
2006
IEEE
The MISP Processor is a programmable media processor which supports multi-issuing, multi-threading and stream processing techniques. MISP executes applications that have been mapp...
146
Voted
ARCS
2010
Springer
15 years 10 months ago
2010
Springer
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
122
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HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...