202 search results - page 9 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
ASPLOS
2000
ACM
13 years 12 months ago
2000
ACM
This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years,...
IISWC
2008
IEEE
14 years 1 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
CF
2007
ACM
13 years 11 months ago
2007
ACM
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...