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DSD
2002
IEEE
96views Hardware» more  DSD 2002»
14 years 16 days ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
ICDE
2009
IEEE
130views Database» more  ICDE 2009»
14 years 9 months ago
Recursive Computation of Regions and Connectivity in Networks
In recent years, the data management community has begun to consider situations in which data access is closely tied to network routing and distributed acquisition: examples includ...
Mengmeng Liu, Nicholas E. Taylor, Wenchao Zhou, Za...
VIS
2006
IEEE
214views Visualization» more  VIS 2006»
14 years 8 months ago
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
Wei Qiao, Michael McLennan, Rick Kennell, David...
DAC
2009
ACM
14 years 8 months ago
Handling complexities in modern large-scale mixed-size placement
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
DAC
1999
ACM
14 years 8 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...