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ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
14 years 11 days ago
Power estimation starategies for a low-power security processor
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling C...
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 12 months ago
Shared reconfigurable architectures for CMPS
This paper investigates reconfigurable architectures suitable for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfi...
Matthew A. Watkins, Mark J. Cianchetti, David H. A...
ERSA
2004
134views Hardware» more  ERSA 2004»
13 years 11 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner
FSKD
2008
Springer
123views Fuzzy Logic» more  FSKD 2008»
13 years 11 months ago
PartSpan: Parallel Sequence Mining of Trajectory Patterns
The trajectory pattern mining problem has recently attracted increasing attention. This paper precisely addresses the parallel mining problem of trajectory patterns as well as the...
Shaojie Qiao, Changjie Tang, Shucheng Dai, Mingfan...
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 10 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija