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» The Logical Execution Time Paradigm
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DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 1 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
FPL
2008
Springer
138views Hardware» more  FPL 2008»
13 years 10 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
RTAS
2008
IEEE
14 years 3 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
PATMOS
2007
Springer
14 years 3 months ago
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models
Abstract. Until now, the great majority of research in low-power systems has assumed a convex power model. However, recently, due to the confluence of emerging technological and ar...
Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Ma...
DATE
2000
IEEE
87views Hardware» more  DATE 2000»
14 years 1 months ago
Multi-Node Static Logic Implications for Redundancy Identification
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...
Kabir Gulrajani, Michael S. Hsiao