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ISCA
1998
IEEE
143views Hardware» more  ISCA 1998»
13 years 12 months ago
Lockup-Free Instruction Fetch/Prefetch Cache Organization
In the past decade. there has been much literature describing various cache organizatrons that exploit general programming idiosyncrasies to obtain maxrmum hit rate (the probabili...
David Kroft
ASPDAC
2010
ACM
150views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Post-silicon debugging for multi-core designs
Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are ...
Valeria Bertacco
ICPR
2004
IEEE
14 years 8 months ago
FPGA based Real-Time Visual Servoing
Real-time image processing tasks not only require high computing power but also high data bandwidth. Though current processors excel in computing power, memory throughput is still...
Jörg Langwald, Mathias Nickl, Stefan Jör...
HPCA
2003
IEEE
14 years 8 months ago
Active I/O Switches in System Area Networks
We present an active switch architecture to improve the performance of systems connected via system area networks. Our programmable active switches not only flexibly route packets...
Ming Hao, Mark Heinrich
SEUS
2009
IEEE
14 years 2 months ago
Towards Time-Predictable Data Caches for Chip-Multiprocessors
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
Martin Schoeberl, Wolfgang Puffitsch, Benedikt Hub...