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HPCA
2009
IEEE
14 years 8 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 8 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
HPCA
2008
IEEE
14 years 8 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...
POPL
2006
ACM
14 years 8 months ago
Engineering with logic: HOL specification and symbolic-evaluation testing for TCP implementations
The TCP/IP protocols and Sockets API underlie much of modern computation, but their semantics have historically been very complex and ill-defined. The real standard is the de fact...
Steve Bishop, Matthew Fairbairn, Michael Norrish, ...
OSDI
2004
ACM
14 years 8 months ago
Automated Worm Fingerprinting
Network worms are a clear and growing threat to the security of today's Internet-connected hosts and networks. The combination of the Internet's unrestricted connectivit...
Sumeet Singh, Cristian Estan, George Varghese, Ste...