Sciweavers

314 search results - page 25 / 63
» The Nachos Instructional Operating System
Sort
View
VLSID
2001
IEEE
144views VLSI» more  VLSID 2001»
14 years 9 months ago
Next Generation Network Processors
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
Deepak Kataria
MICRO
1997
IEEE
79views Hardware» more  MICRO 1997»
14 years 1 months ago
On High-Bandwidth Data Cache Design for Multi-Issue Processors
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
Jude A. Rivers, Gary S. Tyson, Edward S. Davidson,...
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
14 years 1 months ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
DAC
2007
ACM
14 years 9 months ago
A System For Coarse Grained Memory Protection In Tiny Embedded Processors
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no...
Ram Kumar, Akhilesh Singhania, Andrew Castner, Edd...
ASPLOS
2011
ACM
13 years 14 days ago
Mnemosyne: lightweight persistent memory
New storage-class memory (SCM) technologies, such as phasechange memory, STT-RAM, and memristors, promise user-level access to non-volatile storage through regular memory instruct...
Haris Volos, Andres Jaan Tack, Michael M. Swift