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VLSID
2004
IEEE
146views VLSI» more  VLSID 2004»
14 years 9 months ago
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
FSE
1997
Springer
131views Cryptology» more  FSE 1997»
14 years 22 days ago
Fast Software Encryption: Designing Encryption Algorithms for Optimal Software Speed on the Intel Pentium Processor
Most encryption algorithms are designed without regard to their performance on top-of-the-line microprocessors. This paper discusses general optimization principles algorithms desi...
Bruce Schneier, Doug Whiting
ASPLOS
1992
ACM
14 years 20 days ago
High Speed Switch Scheduling for Local Area Networks
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...
Thomas E. Anderson, Susan S. Owicki, James B. Saxe...
IEICET
2008
106views more  IEICET 2008»
13 years 8 months ago
Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Comm
Finite impulse response (FIR) filtering is the most computationally intensive operation in the channelizer of a wireless communication receiver. Higher order FIR channel filters a...
Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund ...
WWW
2007
ACM
14 years 9 months ago
Speeding up adaptation of web service compositions using expiration times
Web processes must often operate in volatile environments where the quality of service parameters of the participating service providers change during the life time of the process...
John Harney, Prashant Doshi