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» The Observational Power of Clocks
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DATE
2009
IEEE
111views Hardware» more  DATE 2009»
16 years 8 days ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb...
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
15 years 10 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
105
Voted
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
15 years 10 months ago
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components
Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malg...
ARVLSI
1999
IEEE
151views VLSI» more  ARVLSI 1999»
15 years 9 months ago
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
Nestoras Tzartzanis, William C. Athas
118
Voted
DAC
1999
ACM
15 years 9 months ago
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style
Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam P...