1542 search results - page 3 / 309 » The Observational Power of Clocks |
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
PATMOS
2005
Springer
14 years 26 days ago
2005
Springer
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
TVLSI
2008
13 years 7 months ago
2008
Recently we proposed a new clocking scheme, injection-locked clocking (ILC), to combat deteriorating clock skew and jitter, and hence reduce power consumption in highperformance mi...
ISVLSI
2002
IEEE
14 years 9 days ago
2002
IEEE
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...