49 search results - page 10 / 10 » The Performance of Cache-Coherent Ring-based Multiprocessors |
ISCA
2000
IEEE
14 years 3 months ago
2000
IEEE
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
ISCA
2007
IEEE
14 years 5 months ago
2007
IEEE
Server consolidation is becoming an increasingly popular technique to manage and utilize systems. This paper develops CMP memory systems for server consolidation where most sharin...
PODC
2010
ACM
14 years 2 months ago
2010
ACM
We study Reader-Writer Exclusion [1], a well-known variant of the Mutual Exclusion problem [2] where processes are divided into two classes–readers and writers–and multiple re...
ISCA
2010
IEEE
14 years 26 days ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...