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ICC
2007
IEEE
139views Communications» more  ICC 2007»
14 years 4 months ago
Joint Power and Channel Minimization in Topology Control: A Cognitive Network Approach
Abstract— Wireless topology control is the process of structuring the connectivity between network nodes to achieve some network-wide goal. This paper presents a cognitive networ...
Ryan W. Thomas, Ramakant S. Komali, Allen B. MacKe...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 3 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
ICCD
2000
IEEE
137views Hardware» more  ICCD 2000»
14 years 2 months ago
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh...
BIRTHDAY
1997
Springer
14 years 2 months ago
Expressive Power of Unary Counters
We compare the expressive power on finite models of two extensions of first order logic L with equality. L(Ct) is formed by adding an operator count{x : ϕ}, which builds a term ...
Michael Benedikt, H. Jerome Keisler
FPL
2006
Springer
219views Hardware» more  FPL 2006»
14 years 1 months ago
FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...
François-Xavier Standaert, Gaël Rouvro...