Sciweavers

4498 search results - page 89 / 900
» The Power of Data
Sort
View
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
15 years 8 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
DAC
2003
ACM
15 years 9 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
RECOMB
2005
Springer
16 years 4 months ago
Very Low Power to Detect Asymmetric Divergence of Duplicated Genes
Abstract. Asymmetric functional divergence of paralogues is a key aspect of the traditional model of evolution following duplication. If one gene continues to perform the ancestral...
Cathal Seoighe, Konrad Scheffler
MOBIHOC
2004
ACM
16 years 3 months ago
A single-channel solution for transmission power control in wireless ad hoc networks
Transmission power control (TPC) has a great potential to increase the throughput of a mobile ad hoc network (MANET). Existing TPC schemes achieve this goal by using additional ha...
Alaa Muqattash, Marwan Krunz
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
16 years 4 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...