In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and t...
— The analysis regarding the impact of the single-step power control (SSPC) scheme on the system performance such as bit error rate, packet error rate and queueing variation is h...
This paper considers MIMO transceivers with linear precoders and decision feedback equalizers (DFEs), with bit allocation at the transmitter. Zero-forcing (ZF) is assumed. Consider...
Ching-Chih Weng, Chun-Yang Chen, P. P. Vaidyanatha...
In this paper, the ergodic sum-rate and outage probability of a downlink single-antenna channel with K users are analyzed in the presence of Rayleigh flat fading, where limited cha...
Bo Niu, Osvaldo Simeone, Oren Somekh, Alexander M....
—A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bi...