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» The Power of the Middle Bit
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ISLPED
2010
ACM
193views Hardware» more  ISLPED 2010»
13 years 8 months ago
PASAP: power aware structured ASIC placement
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
Ashutosh Chakraborty, David Z. Pan
DSD
2006
IEEE
183views Hardware» more  DSD 2006»
14 years 1 months ago
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
Panu Hämäläinen, Timo Alho, Marko H...
KES
2005
Springer
14 years 1 months ago
Reconfigurable Power-Aware Scalable Booth Multiplier
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
Hanho Lee
HCI
2009
13 years 5 months ago
Tonic Changes in EEG Power Spectra during Simulated Driving
Electroencephalographic (EEG) correlates of driving performance were studied using an event-related lane-departure paradigm. High-density EEG data were analyzed using independent c...
Ruey-Song Huang, Tzyy-Ping Jung, Scott Makeig
ISLPED
1999
ACM
160views Hardware» more  ISLPED 1999»
14 years 6 days ago
Mixed-swing quadrail for low power dual-rail domino logic
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
Bharath Ramasubramanian, Herman Schmit, L. Richard...